1. Field of the Invention
The present invention relates to a semiconductor device and a method for producing the same and more particularly, to a LDMOS transistor (lateral double diffusion MOS transistor) and a method for producing the same.
2. Description of the Related Art
The LDMOS transistor has features of being high in switching speed, and being easily used because of an voltage drive system, and it is used for a switching regulator, various kinds of drivers, a DC-DC converter, and the like, taking advantage of the features, so that it becomes a key device in a present power-high breakdown voltage field.
In general, a performance of the LDMOS transistor is represented by a breakdown voltage (yield breakdown voltage) at an off-time and an on resistance. However, they normally have a trade-off relationship, so that it is difficult to realize a high breakdown voltage and a low on resistance. Therefore, development has been made for a long time to realize both of them.
Hereinafter, a description will be made of a conventional LDMOS transistor disclosed in Japanese Unexamined Patent Publication No. 2004-22769 (hereinafter, referred to as the patent document 1). FIGS. 17A and 17B are schematic structure diagrams showing an N channel LDMOS transistor formed on a P type semiconductor substrate, in which FIG. 17A is a top schematic view and FIG. 17B is a cross-sectional schematic view. In addition, FIG. 17B shows a cross-section taken along a line L1-L2 in FIG. 17A. In addition, an interlayer insulation film 15, a source electrode 21, and a drain electrode 22 are not shown in the top schematic view in FIG. 17A, among components shown in FIG. 17B.
As shown in FIGS. 17A and 17B, the conventional N channel LDMOS transistor is provided in such a manner that a P type embedded diffusion region 91 is formed with high energy implantation so as to be continued to a bottom surface of a P type body region 3 formed on a surface of a P type semiconductor substrate 1. A low-concentration N type drift region 5 is formed on the surface of the P type semiconductor substrate 1 so as to be away from the P type body region 3, and the P type embedded diffusion region 91 is formed so that its tip end reaches an inside of the N type drift region 5. FIG. 17A shows a formation region of the P type embedded diffusion region 91 by falling diagonal strokes from to top left to bottom right.
A high-concentration N type source region 6 and a high-concentration P type body contact region 7 are formed on the surface side in the P type body region 3. A high-concentration N type drain region 8 is formed on the part of surface side in the N type drift region 5. In addition, in FIGS. 17A and 17B, the drain region 8 is formed in the drift region 5 on the side opposite to the source region 6 across a field oxide film 11 formed on the drift region 5.
A gate electrode 14 is formed on a gate oxide film 13 formed on the semiconductor substrate 1, and this gate electrode 14 is formed so as to be overlapped commonly on a part of the P type body region 3 and a part of the N type drift region 5. A part of the gate electrode 14 is formed so as to be stranded on the field oxide film 11. Thus, the interlayer insulation film 15 is formed so as to cover the whole surface of the semiconductor substrate 1 including the gate electrode 14.
Thus, the source electrode 21 is formed so as to penetrate the interlayer insulation film 15 and to be in contact with the N type source region 6 and the P type body contact region 7. Similarly, the drain electrode 22 is formed so as to penetrate the interlayer insulation film 15 and to be in contact with the N type drain region 8. The N type source region 6 and the P type body region 3 are electrically at the same potential due to the source electrode 21.
When a breakdown voltage at the time of power-off is measured in the N channel LDMOS transistor, the source electrode 21 and the gate electrode 14 are set to the GND potential, and a plus potential is applied to the drain electrode 22. Thus, when a reverse bias voltage is applied between the drain and the source, an electric field in a depletion layer reaches a critical electric field at a certain voltage, and avalanche breakdown is generated, so that a current starts rapidly flowing between the drain and source. The applied voltage at this time is the breakdown voltage value of the transistor.
In general, when the reverse bias is applied between the drain and the source in the LDMOS transistor, the electric field concentrates around a gate edge (shown by a region A in FIG. 17B) which is provided at an end part of the gate electrode formed on the gate oxide film, on the side of the drain region, which causes the breakdown voltage to be lowered. Therefore, in order to increase the breakdown voltage, it is important to relax the electric field around the gate edge. In addition, when the electric field concentrates around the gate edge, a certain amount of electric charges are left in the gate oxide film 13, which could cause reliability to be lowered. As a result, to relax the electric field around the gate edge is important to improve the reliability of the LDMOS transistor.
Thus, in order to relax the electric field around the gate edge, as described above, the P type embedded diffusion region 91 is provided so as to be continued to the whole bottom surface of the P type body region 3 and the P type embedded diffusion region 91 is formed by high-energy implantation so as to be embedded in the N type drift region 5 in the conventional LDMOS transistor disclosed in the patent document 1. At this time, the P type embedded diffusion region 91 is formed so as to have a concentration higher than that of N type drift region 5.
When the reverse bias is applied between the drain and source in the structure shown in FIGS. 17A and 17B, a depletion layer extends from a joint interface between the P type embedded diffusion region 91 and the N type drift region 5, as described above, but since the concentration of the P type embedded diffusion region 91 is higher than that of the N type drift region 5, the depletion layer easily extends toward the N type drift region 5, so that the whole area of the N type drift region 5 is substantially depleted. As a result, the electric field around the surface including the gate edge (region A) can be sufficiently relaxed. Thus, in a case where the same breakdown voltage is ensured, since the concentration of the N type drift region 5 can be set to be higher, the trade-off relationship between the breakdown voltage and the on resistance of the device can be considerably improved.